Mada za sehemu hiiDemonstrate understanding of the principles of computer architecture and organisationMada 7
- Describe the classification of computer architecture (Von Neumann and Non Von Neumann, Harvard Architecture, Modified Harvard Architecture, Flynn's Taxonomy)
- Demonstrate understanding of Boolean algebra and logic gates (Logic expressions, standard logic gate symbols, logic circuits)
- Explore computer memory (Meaning, design principles, memory hierarchy and interfacing, cache memory, memory mapping, primary & secondary memory)
- Analyse instruction set architecture (Instruction set types, registers, instruction execution cycles, addressing modes, register transfer language, ARM and x86 architectures)
- Describe I/O system (Direct Memory Access, Interrupt and exception, privileged / non privileged instruction)
- Demonstrate function of memory and input-output system
- Develop understanding of pipelining (Basics, types, stalling & forwarding, throughput and speedup, hazards) and Instruction Level Parallelism (concept, compilation techniques, scalar versus superscalar pipelining, branch prediction, register renaming) and thread and data level parallelism
Instruction Set Architecture
Instruction Set Architecture (ISA) defines the interface between software and hardware, specifying the instructions a processor can execute, the registers available, and how data is accessed. Understanding ISA enables programmers to write efficient code and system designers to optimise computer systems for specific tasks.
ISA serves as a contract between programmers and the processor. It defines:
- Instruction formats: How instructions are encoded in binary
- Instruction types: The operations the CPU can perform
- Addressing modes: How instructions locate their operands
- Register set: The available CPU registers
- Data types: The sizes and formats of data that can be processed
The kitchen analogy from the textbook helps clarify ISA: just as a chef follows recipes with detailed instructions, a processor executes instructions defined by the ISA. Registers are like chef's tools, addressing modes are like cooking techniques, and the instruction execution cycle mirrors the step-by-step cooking process.
Intel x86
A widely used CISC architecture for personal computers and servers. It supports both complex and simple instructions, offering versatility. Examples: Intel Celeron, Pentium, Core i3/i5/i7.
ARMv8 (AArch64)
A RISC architecture offering both 32-bit and 64-bit instruction sets, known for energy efficiency. Used in: Apple A13/A14/A15 Bionic, Qualcomm Snapdragon, Samsung Exynos, Amazon Graviton2 servers.
RISC-V
An open-source RISC architecture gaining popularity for IoT applications due to its flexibility. Powers NVIDIA Grace CPU and SiFive Core IP.
Custom ISAs
Tailored for specific applications like machine learning or network processing, combining RISC and CISC elements for optimal performance.
(a) Arithmetic Logic Unit (ALU) Instructions
Perform mathematical and logical operations:
- Arithmetic: add, sub, mul, div
- Logical: and, or, xor, not
- Shift: shl, shr
- Compare: cmp, eq, gt, lt
(b) Data Transfer Instructions
Move data between locations:
- Load: lw (load word), lb (load byte) — memory to register
- Store: sw (store word), sb (store byte) — register to memory
- Move: mov — register to register
- I/O: in, out — CPU to external devices
(c) Control Flow Instructions
Control program execution:
- Branch: if, else, goto — conditional execution
- Jump: jmp — unconditional jump
- Call: call — subroutine invocation
- Return: ret — return from subroutine
(d) System Control Instructions
Interact with operating system (privileged):
- Interrupt handling
- Memory management
- Processor control
(e) Special Instructions
Purpose-specific instructions:
- Floating-point operations
- String manipulation
- Vector processing
Registers are high-speed memory locations within the CPU that temporarily hold data being processed.
Classification of Registers
(a) General Purpose Registers (GPRs) Versatile storage locations usable by any instruction. Store integers, floating-point numbers, or memory addresses during execution.
(b) Special Purpose Registers (SPRs) Dedicated to specific CPU control functions:
| Register | Function |
|---|---|
| Program Counter (PC) | Tracks next instruction address |
| Stack Pointer (SP) | Manages function calls and local variables |
| Status Register (SR) | Holds flags (carry, zero, overflow) for conditional operations |
Functions of CPU Registers
- Data storage and manipulation: Temporary holding ground for data being processed
- Performance improvement: Reduce need to fetch from slower main memory
- Facilitate function calls: Pass arguments through registers
- Conditional branching: Status flags enable program flow control
Register Operations Examples
RISC-V: add a0, a1, a2
- Adds contents of a1 and a2, stores result in a0
ARMv8: ldr x0, [x1]
- Loads data from memory address in x1 into x0
x86: mov eax, [ebx + 4]
- Fetches value from memory location (ebx + 4) into eax
The CPU follows a five-phase cycle to execute each instruction:
(a) Fetch
- Program Counter (PC) holds address of next instruction
- Control Unit reads memory location pointed by PC
- Instruction loaded into Instruction Register (IR)
- PC incremented to point to next instruction
(b) Decode
- Control Unit analyzes the instruction in IR
- Breaks down into opcode and operands
- Identifies source (rs) and destination (rt) registers
- Generates control signals for next phase
(c) Read Operands
- Control Unit locates registers identified during decode
- Values loaded into temporary holding registers
- For ALU operations, operands are fetched from registers
(d) Execute
- ALU activated based on opcode
- Performs the operation (e.g., addition for "add" instruction)
- Result stored in temporary register
(e) Write Back
- Result transferred to destination register
- For memory instructions, data written to memory
- PC updated to continue program execution
Worked Example: Executing add r1, r2, r3
Given: r2 = 5, r3 = 6
| Phase | Action | Result |
|---|---|---|
| Fetch | Load instruction from memory | IR = add r1, r2, r3 |
| Decode | Identify operation and registers | Opcode = add, rs=r2, rt=r3, rd=r1 |
| Read Operands | Load values from r2 and r3 | r2 = 5, r3 = 6 |
| Execute | ALU performs addition | Result = 11 |
| Write Back | Store result in r1 | r1 = 11 |
Addressing modes specify how instructions locate their operands.
(a) Register Addressing
Data is in CPU registers — fastest access.
MIPS Example: add $t1, $s2, $s3
- Adds values in s3, stores in $t1
(b) Immediate Addressing
Instruction contains actual data value.
MIPS Example: addi $t0, $s1, 5
- Adds immediate value 5 to t0
(c) Direct Addressing
Instruction specifies memory address where data is stored.
MIPS Example: lw $t2, 10($s0)
- Loads from memory address (address in $s0 + 10)
(d) Indirect Addressing
Instruction specifies address that points to another address containing data.
MIPS Example: lw $t4, ($s5)
- Loads from memory location pointed to by address in $s5
(e) Relative Addressing
Instruction specifies offset from current instruction address.
MIPS Example: beq $t6, $s7, Label
- Branches to Label if s7, using offset from PC
RTL is a symbolic notation describing data flow between registers and functional units within a digital system.
Common RTL Symbols
| Symbol | Meaning | Example |
|---|---|---|
| Letters | Registers | MAR, PC, IR |
| ← | Transfer of information | R3 ← R2, PC ← PC + 1 |
| , | Two micro-operations | R3 ← R2, R5 ← R4 |
| : | Conditional operation | T:R2←R1 if T=1 |
| () | Part of a register | R1(0-7) |
RTL Micro-operations Examples
Arithmetic: R1 + R2 → R3
- Add contents of R1 and R2, store result in R3
Logical: R1 AND R2 → R3
- Perform AND operation on R1 and R2, store in R3
Data Transfer: R2 ← R1
- Move contents of R1 to R2
Shift: R1 ← R1 << 1
- Shift R1 left by one bit
ARM (Advanced RISC Machine)
- Type: RISC (Reduced Instruction Set Computing)
- Design philosophy: Simpler, fewer instructions for energy efficiency
- Applications: Mobile devices (smartphones, tablets), embedded systems
- Advantages: Lower power consumption, heat generation
- Example processors: Apple A-series, Qualcomm Snapdragon, Samsung Exynos
x86
- Type: CISC (Complex Instruction Set Computing)
- Design philosophy: Rich instruction set for complex operations
- Applications: Desktop computers, laptops, servers
- Advantages: Wide software compatibility, handles complex tasks efficiently
- Example processors: Intel Core i3/i5/i7, AMD Ryzen
Comparison Table
| Characteristic | ARM Cortex-A8 | Intel Core i7 |
|---|---|---|
| Architecture | Von Neumann | Von Neumann |
| ISA | ARMv7 | x86-64 |
| Cache | L1: 32KB, L2: 128KB-1MB | L1: 32KB, L2: 256KB, L3: 8MB |
| Power consumption | Lower | Higher |
| Typical applications | Mobile devices | Desktops, laptops, servers |
In Tanzania, mobile money transactions (such as M-Pesa) rely on processors executing instruction sets to process payments. When a farmer in Mbeya sells vegetables and receives payment via mobile money, the phone's ARM-based processor uses its instruction set to fetch the transaction instruction from memory, decode it, and execute the transfer operation — processing the data using registers within the CPU and updating the account balance stored in memory. Understanding ISA helps software developers optimize mobile banking applications to run efficiently on low-cost Tanzanian smartphones with limited processing power.
Swali
Which phase of the instruction execution cycle involves the Arithmetic Logic Unit (ALU) performing the actual computation?
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